1. Field of the Invention
The present invention relates to a digital communication receiver and a digital communication transmitter-receiver both suitable for use in satellite communications, mobile communications and mobile satellite communications.
2. Description of the Related Art
As a conventional clock recovery circuit, there is known one disclosed in a technical literature "Application for Digital Signal Processing" by The Institute of Electronics and Communication Engineers, p. 169, for example. FIG. 16 shows a system in which the clock recovery circuit has been subjected to digital PLL, i.e., a system called "zero cross method".
In FIG. 16, there are shown an input terminal 1 for inputting a received signal, a demodulator 2 for demodulating the received signal, a phase comparator 3 for detecting a difference in phase between a clock outputted from a variable divider 6 and a symbol clock component included in the received signal from an output produced from the demodulator 2, a random walk filter 4 for averaging outputs produced from the phase comparator 3, a fixed frequency oscillator 5 for oscillating at a frequency of an integral multiple of the symbol clock component included in the received signal, the variable divider 6 for dividing an output produced from the fixed frequency oscillator 5 at a division ratio corresponding to an output produced from the random walk filter 4 and outputting a clock synchronized with the symbol clock included in the received signal to each part, and a clock regenerating circuit 100 composed of the random walk filter 4, the fixed frequency oscillator 5 and the variable divider 6.
FIG. 17 is a block diagram showing one example of a configuration of a phase comparator. In FIG. 17, there are shown an input terminal 10 for inputting one bit corresponding to an MSB (Most Significant Bit) of a signal outputted from the demodulator 2, an input terminal 11 for inputting a clock outputted from the variable divider 6, an invertor 12 for inverting the output supplied from the input terminal 11, a first latch circuit 13 for latching the signal inputted from the input terminal 10 based on a clock outputted from the inversion circuit 12, a second latch circuit 14 for latching the signal inputted from the input terminal 10 based on the input clock supplied from the input terminal 11, third and fourth latch circuits 15 and 16 for respectively latching outputs produced from the first and second latch circuits 13 and 14 based on the clocks input from the input terminal 11, an exclusive-OR circuit 17 for XORing outputs supplied from the third and fourth latch circuits 15 and 16, an output terminal 18 for outputting a signal outputted from the exclusive-OR circuit 17 to the outside, an exclusive-OR circuit 19 for XORing the signals outputted from the second and fourth latch circuits 14 and 16, and an output terminal 20 for outputting a signal outputted from the exclusive-OR circuit 19 to the outside.
FIG. 19 is a block diagram showing one example of a configuration of the random walk filter 4. In FIG. 19, there are shown an input terminal 30 for inputting the output supplied from the output terminal 18, an input terminal 31 for inputting the output supplied from the output terminal 20, an input terminal 32 for outputting the clock outputted from the variable divider 6, a 2N step up/down counter 33 which is activated in response to the clock supplied from the input terminal 32, counts UP/DOWN in response to the signal inputted from the input terminal 30 and performs enable/disable operations in response to the signal inputted from the input terminal 31, an output terminal 34 for outputting a "Retard" signal when a value counted by the 2N step up/down counter 33 is 2N, an output terminal 35 for outputting an "Advance" signal when the value counted by the 2N step up/down counter 33 is 0, and an N setting circuit 36 for setting the count of the 2N step up/down counter 33 to a value N when either the "Retard" signal or the "Advance" signal is outputted.
FIG. 20 is a block diagram showing one example of a configuration of the variable divider 6. In FIG. 20, reference numeral 40 indicates an input terminal for inputting a "Retard" signal. Reference numeral 41 indicates an input terminal for inputting an "Advance" signal. Reference numeral 42 indicates a pulse adding/eliminating circuit for adding a pulse to the output of the fixed frequency oscillator 5 and eliminating it therefrom in response to the signal inputted from the input terminal 40 and the signal inputted from the input terminal 41 respectively. Reference numeral 43 indicates a divider for dividing an output produced from the pulse adding/eliminating circuit 42. Reference numeral 44 indicates an output terminal for outputting an output produced from the divider 43 to the outside.
The operation of the zero cross method shown in FIG. 16 will be described below. According to the present zero-cross method, the phase of the clock outputted from the variable divider 6 is controlled so that an average value of zero cross point data (1, 0) sampled based on the clock outputted from the variable divider 6 becomes "0.5", thereby phase-synchronizing the clock outputted from the variable divider 6 with the symbol clock component included in the received signal. The received signal inputted from the input terminal 1 is demodulated by the demodulator 2.
A sign bit (MSB: {1, 0}) represented in the form of a baseband waveform, of the output of the demodulator 2 is inputted to the phase comparator 3. In the phase comparator 3, the first latch circuit 13 samples data near a zero cross point from the signal inputted from the input terminal 10 and the second latch circuit 14 samples data near a Nyquist point from the signal. Further, the outputs of the first and second latch circuits 13 and 14 are latched in their corresponding third and fourth latch circuits 15 and 16 with timing of the clock inputted to the input terminal 11. At the same time the second latch circuit 1 4 samples data near the next Nyquist point.
FIG. 18(a) shows one example of a sample of a baseband signal. The present example shows a case where data varies from +1 to -1. FIG. 18(b) illustrates a waveform at the time that a soft decision signal in FIG. 18(a) is regarded as a hard decision {1, 0}. In this case, the second latch circuit 14 latches therein data near a Nyquist point at a time (m+1), the third latch circuit 15 latches therein data near a zero cross point at a time (m+(1/2)) and the fourth latch circuit 16 latches therein data near a Nyquist point at a time (m).
The exclusive-OR circuit 17 multiplies the output of the third latch circuit 15, i.e., zero cross point information at the time (m+(1/2)) by the output of the fourth latch circuit 16, i.e., Nyquist point information at the time (m) and outputs the result of multiplication from the output terminal 18. This is made because when the data changes from -1 to +1 and from +1 to -1, the sign of an error in clock phase and that of phase error information due to zero cross are made coincident with each other.
The output supplied from the output terminal 18 corresponds to "lead/lag" information about the clock and is controlled so that the average of output values becomes zero, i.e., "0.5" in the form of a sign bit (0, 1). In the present example, "0" is represented as an output in the case of "lead", whereas "1" is represented as an output in the case of "lag".
Further, the exclusive-OR circuit 19 XORs the output of the second latch circuit 14, i.e., Nyquist point information at the time (m+1) and the output of the fourth latch circuit 16, i.e., Nyquist point information at the time (m) and outputs the result of XORing from the output terminal 20.
When data remains unchanged between consecutive Nyquist points, zero cross point information produced during that time is made insignificant. It is therefore determined using the original signal whether the zero cross point information outputted from the output terminal 18 is "significant/insignificant".
In the present embodiment, "1" is outputted when the zero cross point information is "significant" and "0" is outputted when the zero cross point information is "insignificant".
Thus, the phase comparator 3 outputs the "lead" signal of "0" when the phase of the clock outputted from the variable divider 6 leads the zero cross point (or Nyquist point) and outputs the "lag" signal of "1" when the phase of the clock lags behind the zero cross point. And simultaneously, the signal which represents a "significant/insignificant" for "lag/lead" signal is outputted.
Next, the random walk filter 4 averages phase difference information on the output data produced from the phase comparator 3. The 2N step up/down counter 33 counts up/down based on the clock inputted from the input terminal 32 when the signal inputted from the input terminal 31 is "1", i.e., only when the output data of the phase comparator 3 is regarded as "significant". When the signal inputted from the input terminal 30 is "0", the count of the 2N step up/down counter 33 is incremented by one. On the other hand, when the signal is "1", the count is decremented by one.
Thus, when the value counted by the 2N step up/down counter 33 is brought to "2N", the 2N step up/down counter 33 outputs a "Retard" signal from the output terminal 34 and at the same time the N setting circuit 36 sets the count of the 2N step up/down counter 33 to a central value "N".
When the count is brought to "0", the 2N step up/down counter 33 outputs an "Advance" signal from the output terminal 35 in the same manner as described above and at the same time the N setting circuit 36 sets the count of the 2N step up/down counter 33 to the central value "N". Thus, the signal outputted from the phase comparator 3 is averaged by the 2N step up/down counter 33.
Next, the "Advance" and "Retard" signals outputted from the random walk filter 4 are inputted to the variable divider 6. An oscillating frequency of the fixed frequency oscillator 5 is normally selected to an integral multiple of a symbol rate.
If the symbol rate is represented as f.sub.S (Hz) and the frequency outputted from the fixed frequency oscillator 5 is represented as f.sub.OSC (Hz), then the following relationship is given: EQU f.sub.OSC (Hz)=M f.sub.S (Hz) ( M: integer) (1)
When no signals are inputted from the input terminals 40 and 41, the signal outputted from the fixed frequency oscillator 5 passes through the pulse adding/eliminating circuit 42 and is inputted to the divider 43, which divides the frequency of the signal by M. Thus, the frequency-divided symbol rate (f.sub.S) clock is outputted from the divider 43.
When the "Retard" signal is inputted from the input terminal 40, the pulse adding/eliminating circuit 42 eliminates clock pulse corresponding to one period from the clock signal outputted from the fixed frequency oscillator 5. As a result, the phase of the clock outputted from the divider 43 is delayed by a (1/M) period from the previous phase. On the other hand, when the "Advance" signal is inputted from the input terminal 41, the pulse adding/eliminating circuit 42 adds the clocks corresponding to the one period to the clock signal outputted from the fixed frequency oscillator 5. As a result, the phase of the clock outputted from the divider 43 leads the previous phase by the (1/M) period. The clock signal outputted from the divider 43 is phase-controlled based on the signals inputted from the input terminals 40 and 41 in this way.
Thus, the clock recovery circuit 100 using the "zero cross method" shown in FIG. 16 allows the clock outputted from the variable divider 6 to be phase-synchronized with the symbol clock component included in the received signal.
FIG. 21 is a view showing a configuration of a loop filter employed in the conventional secondary loop clock regenerating circuit. This loop filter is effective where a clock frequency offset corresponding to a difference between a frequency f.sub.RX (Hz) of the symbol clock component included in the received signal and a free-running frequency f.sub.S =(f.sub.OSC)/M(Hz) of the clock regenerating circuit exists.
In this case, the random walk filter 4 in the clock regenerating circuit 100 shown in FIG. 16 is partly changed as shown in FIG. 21.
Owing to such a secondary loop configuration, steady-state phase error produced due to the clock frequency offset developed in the primary loop configuration can be reduced. Incidentally, the secondary loop digital PLL has been described in a technical magazine "How to use PLL IC" published by Akiba publisher, p. 154, for example. The steady-state phase error has been described on page 26 in the same technical magazine.
In FIG. 21, there are shown an input terminal 50 for inputting a signal outputted from the phase comparator 3, an input terminal 51 for inputting a clock outputted from the variable divider 6, a code changing circuit 52 for converting a lead/lag signal (0, 1) to (-1, +1) when a "significant/insignificant" signal corresponding to the signal inputted to the input terminal 50 indicates "significant" and outputting "0" when the signal indicates "insignificant", an, adder 53 for adding an output value of the code changing circuit 52 and an output value of a latch circuit 54, a latch circuit 54 for latching an output value of the adder 53 therein in response to the clock inputted to the input terminal 51, a first integrator 55 comprising the adder 53 and the latch circuit 54, an adder 56 for adding an output value of the first integrator 55 and an output value of a latch circuit 57, the latch circuit 57 for latching an output value of the adder 56 therein in response to the clock inputted to the input terminal 51, a second integrator 58 composed of the adder 56 and the latch circuit 57, a comparator 59 for outputting a "Retard" signal or an "Advance" signal when the absolute value of a value outputted from the second integrator 58 is beyond a given value (e.g., when the integrator 58 is brought to overflow or underflow), an adder 60 for adding a signal outputted from the random walk filter 4 and the signal outputted from the comparator 59, and an output terminal 61 for outputting the output of the adder 60 to the outside.
The operation of the clock recovery circuit 100 shown in FIG. 16 at the time when the random walk filter 4 of the clock recovery circuit 100 is partially changed as shown in FIG. 21, will now be described.
The output of the phase comparator 3 shown in FIG. 16 is divided into the "lead/lag" signal and the "significant/insignificant" signal, one of which is inputted to the random walk filter 4 and the other of which is inputted to the code changing circuit 52. The random walk filter 4 is activated as described above to output the "Advance/Retard" signal. On the other hand, the code changing circuit 52 outputs "0" when the "significant/insignificant" signal indicates "insignificant", outputs "+1" when the "significant/insignificant" signal indicates "significant" and the "lead/lag" signal indicates "lead" and outputs "-1" when the "significant/insignificant" signal indicates "significant" and the "lead/lag" signal indicates "lag". A value (0, .+-.1) outputted from the code changing circuit 52 is inputted to the first integrator 55 and is subjected to integral processing for each output clock of the variable divider 6. Further, the signal outputted from the first integrator 55 is integrated by the second integrator 58.
When a frequency offset .DELTA.f(Hz) corresponding to a difference between a symbol clock component frequency f.sub.RX (Hz) included in a received signal and a free-running frequency f.sub.S (Hz) of the clock recovery circuit now exists, a numeric value (.DELTA.f information) corresponding to the frequency deviation .DELTA.f(Hz) is stored in the latch circuit 54.
The .DELTA.f information is integrated by the second integrator 58 and exceeds a threshold value of the comparator 59 at substantially constant intervals. The comparator 59 outputs an "Advance/Retard" signal therefrom. FIG. 22 shows, as one example, an output value of the second integrator 58 at the time when the .DELTA.f information is a positive value and the manner in which the comparator 59 outputs the "Retard" signal.
When the output value (.DELTA.f information) of the first integrator 55 is now correct, the comparator 59 outputs the "Retard" signal so as to compensate for a phase shift produced due to the frequency deviation. Therefore, the "lead/lag" signal outputted from the phase comparator 3 is generated substantially at the same frequency.
As a result, the output value of the first integrator 55 is maintained at the present value on the average. In this condition, the symbol clock outputted from the variable divider 6 is phase-synchronized with the frequency f.sub.RX (Hz) of the symbol clock component included in the received signal.
Thus, even when the frequency offset .DELTA.f(Hz) corresponding to the difference between the symbol clock component frequency f.sub.RX (Hz) included in the received signal and the free-running frequency f.sub.S (Hz) of the clock recovery circuit exists, the phase synchronization can be performed without the stationary phase error owing to the secondary loop configuration shown in FIG. 21.
A configuration of a loop filter employed in a clock recovery circuit at the time that a signal to be received is intermittently input as in the case of a TDMA (Time Division Multiple Access) system, a TDM (Time Division Multiplex) system and VOX (Voice Operated Transmission) control on SCPC (Single Carrier Per Channel), is shown in FIG. 23.
In the same drawing, components having the same functions as those shown in FIG. 21 are identified by the same symbols. Reference numeral 65 indicates an input terminal for inputting a gate signal to the loop filter. Reference numeral 66 indicates a random walk filter whose operation is controlled by the gate signal. Reference numeral 67 indicates a third integrator constructed so that a gate terminal is added to the first integrator 55 and whose operation is controlled by the gate signal. Reference numeral 68 indicates a fourth integrator constructed so that a gate terminal is added to the second integrator 58 and whose operation is controlled by the gate signal.
The operation of the loop filter shown in FIG. 23 will now be described. When a signal to be received is intermittently input as shown in FIG. 24(a), the clock recovery circuit malfunctions due to only noise components other than the received signal upon operating the clock recovery circuit at all times.
In order to avoid such a malfunction, a gate signal shown in FIG. 24(b), which is rendered "LOW" only during reception, is inputted from the input terminal 65 and the loop filter (corresponding to the random walk filter 66, the third integrator 67 and the fourth integrator 68 in FIG. 23) of the clock recovery circuit is rendered "HOLD" as shown in FIG. 24(c) when no received signal exists. The entirety of the clock recovery circuit is brought into a free-running state in this way. Thus, the clock recovery circuit is normally activated under the presence of the received signal and is free-run under the absence of the received signal, thereby making it possible to prevent the clock recovery circuit from taking in the noise alone and malfunctioning.
However, when the frequency offset .DELTA.f(Hz) corresponding to the difference between the symbol clock component frequency f.sub.RX (Hz) included in the received signal and the free-running frequency f.sub.S (Hz) of the clock recovery circuit exists and a non-reception time interval is long, i.e., a time interval necessary for the clock recovery circuit to freely run is long, a problem arises that a phase shift occurs due to the frequency offset .DELTA.f(Hz) and the clock recovery circuit is rendered asynchronous upon the next reception.
FIGS. 25(a), 25(b) and 25(c) respectively illustrate examples of received signals obtained during continuous reception, reception of 3ch TDM signals and intermittent reception.
During continuous reception and reception of 3ch TDM signals as shown in FIGS. 25(a) and 25(b), the clock recovery circuit can hold synchronization. However, when a non-reception time interval is very long as during intermittent reception shown in FIG. 25(c), the clock recovery circuit cannot hold synchronization.
The receiver and transmitter-receiver each having the conventional clock recovery circuit are constructed as described above. In the receiver and transmitter-receiver described above, a problem arises that when the frequency offset corresponding to the difference between the symbol clock component frequency included in the received signal and the free-running frequency of the clock recovery circuit exits and the non-reception time interval is very long, the clock recovery circuit cannot maintain phase synchronization. Another problem arises that when the control unit is operated based on the clock outputted from the clock recovery circuit, the control unit cannot maintain phase synchronization. A further problem arises that when a signal to be transmitted is generated using each clock outputted from the control unit, the accuracy of generating the signal to be transmitted, based on the clock is lowered.